Electronics & Communication Engineer
Designing silicon. Building intelligent hardware.
VLSI Design · Embedded Systems · AI Accelerators · Electrochemical Sensors
IIT Kharagpur Intern · CBIT Class of 2027 · NPTEL Elite Gold
Bridging silicon design and experimental sensing.
I'm a fourth-year ECE student at Chaitanya Bharathi Institute of Technology, Hyderabad, working at the intersection of hardware design and real-world sensing systems. My core focus is VLSI — from RTL design in Verilog to physical design flows using Cadence Virtuoso.
I did Summer Research Intern at IIT Kharagpur's SWAN Lab, working on hardware-oriented research under Prof. Sudip Misra. In parallel, I'm building HARMOMETER — a custom ESP32-based potentiostat for detecting uric acid and urea in saliva.
I hold NPTEL Elite Gold certifications (Top 1%) in System Design through Verilog, Microsensors & Nanosensors, and Cloud Computing. I was selected for the Samsung Semiconductor Fellowship at IISc Bangalore.
GPA
9.28 CGPA
(Up to Semester VI)
INSTITUTE
CBIT ECE '27
RESEARCH
IIT KGP Intern
HONOR
NPTEL Elite Gold
Things I've Built
HARMOMETER
ESP32 Electrochemical Potentiostat
Custom IoT potentiostat for non-invasive detection of uric acid and urea in saliva using Square Wave Voltammetry (SWV) and Linear Sweep Voltammetry (LSV). Full signal chain: ESP32 → MCP4725 DAC → OPA2333 control amp → electrochemical cell → ADS1115 ADC. Includes a Wi-Fi web dashboard and BLE Flutter Android app.
INT8 Matrix Multiplication Engine
CompletedAI Accelerator — RTL to GDSII
Designed a systolic array-based INT8 matrix multiplication engine in Verilog HDL targeting AI inference acceleration. Completed full RTL-to-GDSII physical design flow including synthesis, floorplanning, placement, and routing with Cadence Virtuoso. Optimized for PPA metrics.
FPGA Delta-Sigma Modulator
CompletedDigital DAC on Spartan-7
Engineered a first-order Digital-to-Analog Converter entirely in the digital domain on a Spartan-7 FPGA. Implemented digital integrators and 1-bit quantizers achieving noise shaping and oversampling at 100 MHz. Used Pulse Density Modulation (PDM) to emulate analog voltage levels without external filtering.
Multilingual Speech-to-Speech System
CompletedReal-time translation across 12 languages
Built a real-time speech-to-speech translation pipeline supporting 12 languages using LangChain and Azure OpenAI. Deployed during Infosys Springboard internship to enhance accessibility on OTT platforms.
Where I've Worked
NPTEL Summer Intern
IIT Kharagpur — SWAN Lab
- ›Selected for a 12-week in-person summer internship under Prof. Sudip Misra at the SWAN Lab.
- ›Working on potentiostat and contributing to hardware-oriented research initiatives.
Project Intern — VLSI & FPGA
Chips to Startup (C2S) Program
- ›Selected for the MeitY-backed C2S initiative focused on semiconductor design flows and FPGA prototyping.
- ›Gained hands-on experience in RTL design, simulation, and hardware validation using Xilinx Vivado tools.
- ›Implemented a Delta-Sigma Modulator DAC on Spartan-7 FPGA using Verilog HDL.
Project Intern — Generative AI
Infosys Springboard
- ›Developed a multilingual Speech-to-Speech translation system supporting 12 languages.
- ›Used LangChain and Azure OpenAI for real-time NLP and translation pipelines.
- ›Targeted accessibility improvement for OTT platform users across language barriers.
Technical Stack
RTL & Physical Design
Embedded Systems & Firmware
Software & Scripting
EDA & Simulation
Recognition & Certifications
Samsung Semiconductor Workforce Development Program (ISWDP)
Issuer: Samsung Semiconductor India • IISc Bangalore
Elite Gold — System Design through Verilog
Issuer: NPTEL (IIT)
Elite Gold — Microsensors & Nanosensors
Issuer: NPTEL (IIT)
Elite Gold — Google Cloud Computing Foundation
Issuer: NPTEL (IIT)
Elite Silver — VLSI Design Flow: RTL to GDS
Issuer: NPTEL (IIT)
Let's Connect
Open to research internships, VLSI/embedded roles, and collaboration on hardware projects.